Greater China Semiconductors: Double Catalysts from Memory Expansion and Huawei’s t (τ)-Law

Core Conclusion

China’s wafer fab equipment (WFE) market is entering a phase of dual acceleration. Memory capacity builds at YMTC and CXMT are being pulled forward sharply, while Huawei’s recently published τ-scaling framework—and its production-proven LogicFolding implementation—creates a new structural demand vector for 3D IC tools. The combination lifts 2026–27 China WFE growth to 15–18% Y/Y, to US$48bn and US$56bn. We raise price targets on Naura, AMEC, and ACMR, keeping Overweight ratings on all three; the primary upside drivers are memory-driven order books and the emerging hybrid bonding / TSV equipment requirement stemming from Huawei’s architecture.

Memory Capex Acceleration

YMTC has moved Fab 3 into construction and will begin ramping in 2026, with Fabs 4 and 5 now on the roadmap. CXMT is adding a Shanghai site on top of its existing Hefei and Beijing fabs. Our revised bottom‑up capacity forecasts: YMTC reaches 85 kwpm in 2027 and 100 kwpm in 2028; CXMT reaches 80 kwpm in 2026, 90 kwpm in 2027, and 100 kwpm in 2028. At the macro level, the global WFE market is now projected at US$149bn in 2026 (+27% Y/Y) and US$191bn in 2027 (+28% Y/Y), with China accounting for a stable one‑third share.

Investment implication: The step‑up in memory capex translates directly into higher domestic tool demand for etch, deposition, and clean—segments where Naura and AMEC are gaining share. The capacity trajectory implies that 2026–27 equipment orders from memory customers will land well above current consensus revenue estimates for these names.

Huawei’s τ‑Law and the 3D IC Catalyst

On May 25, Huawei published a research paper introducing τ‑scaling theory and LogicFolding, a technique that vertically integrates circuit layers during wafer manufacturing to reduce interconnect lengths and lower latency. In practice, this allows 5nm/7nm‑class chips to deliver performance that rivals more advanced nodes—potentially circumventing node‑access restrictions. Hybrid bonding and through‑silicon via (TSV) metallization are repeatedly cited as critical enablers.

Investment implication: The architecture generates incremental demand for hybrid bonding systems and TSV copper electrochemical plating (ECP). ACMR’s non‑wet cleaning tool business—specifically its ECP platform for TSV—is a direct beneficiary. More broadly, any Chinese logic maker adopting this 3D IC path will need to invest in corresponding WFE, extending the duration of China’s equipment up‑cycle beyond the memory build‑out alone.

Key Risks

• US export controls: Tighter restrictions on advanced deposition, etch, or bonding tools could disrupt capacity expansion plans, especially for 3D IC production.
• Memory cycle: A downturn in NAND/DRAM pricing would slow the pace of capacity additions and capex approvals.
• Technology execution: Huawei’s LogicFolding is production‑proven at limited scale; high‑volume yield, cost, and throughput data are not yet public.
• Customer concentration: ACMR, Naura, and AMEC each have meaningful exposure to a small number of large domestic fabs, amplifying the impact of any single client’s spending pause.

Valuation and Trade Implications

• Naura (002371.SZ): Price target raised to Rmb818, reflecting higher memory‑driven orders and market‑share gains in etch/deposition.
• AMEC (688012.SS): Price target to Rmb550, supported by robust localization demand from YMTC and CXMT.
• ACMR (ACMR): Price target to US$90, incorporating stronger ECP demand from memory clients and the new TSV metallization opportunity opened by Huawei’s 3D IC adoption.

All three remain Overweight. The next catalysts are equipment order disclosures from major memory fabs in 2H26 and initial tool tenders linked to Huawei’s 3D IC supply chain.