Ming-Chi Kuo (郭明錤)

Some quick thoughts on Intel's EMIB-T packaging for the new 2H27 Google TPU (Humufish). Based on my industry checks: 【How to read EMIB-T's 90% yield?】 1. Given Intel's track record running EMIB in mass production, hitting 90% technology validation yield on EMIB-T (still under development) is a very positive but reasonable data point. 2. Intel benchmarks EMIB production/assembly yield against FCBGA. Industry FCBGA yield today is generally above 98%. 3. On yield, getting from 90% to 98% is harder than getting from project kickoff to 90%. And technology validation yield ≠ final production yield, especially with some Humufish specs still unfinalized. So long-term, I'm positive on Intel's advanced packaging story. Near to mid-term, I'm staying cautious on how they get there. 【From 90% to 98%. Looks like just a few points. Does Google care? Absolutely】 1. Google recently asked TSMC how much it could save by placing wafer orders for Humufish's main compute die (designed in-house by Google) directly, rather than routing them through MediaTek. 2. Google and MediaTek have run a semi-COT model since day one (8t). MediaTek's mark-up sits mostly on the parts it designs itself, so whether Google places the wafer orders for main compute die directly isn't a key swing factor for MediaTek's earnings trajectory. 3. But Google even probing whether it can squeeze out the pass-through mark-up on wafer orders tells you something: Google has shifted from easygoing buyer to hard-nosed on cost. The reason is simple: to take on Nvidia head-on, cost is Google's edge, which makes EMIB-T production yield Google's problem to solve. For context, TSMC's yield target on 5.5-reticle CoWoS in 2026 also starts at 98%. 【TSMC's position】 1. My understanding is TSMC is still working out how much advanced-node capacity to allocate to Humufish in 2H27, for two reasons: (1) it still wants the back-end packaging orders, though looks unlikely for now, and that's by design on Google's part; and (2) it's still gauging actual back-end output from EMIB-T, to avoid misallocating scarce advanced-node capacity. 2. Humufish's effective back-end output hinges on both EMIB-T and substrates, and both need to be tracked together. 3. On the Humufish semi-COT model, TSMC also prefers MediaTek to place the wafer orders for the main compute die. Beyond the close working relationship, the key point is MediaTek is TSMC's third-largest advanced-node customer in 2025. If TPU orders shift, MediaTek's scale makes it a natural buffer for TSMC to rebalance its wafer allocation mix.

閒聊 Intel EMIB-T 封裝的 2H27 新款 Google TPU（Humufish）。以下根據我的產業調查： 【EMIB-T 90% 良率，該怎麼看？】 1. 基於 Intel 已經有穩定生產 EMIB 的經驗，開發中的 EMIB-T 技術驗證良率達到 90%，是很正向但也合理的訊號。 2. Intel 把 FCBGA 設定為 EMIB 生產（組裝）良率的比較標竿。目前業界 FCBGA 的生產良率約在 98% 以上。 3. 從良率角度，90%→98% 難度高於從開案 → 90%。此外，技術驗證良率與成品生產良率也是兩回事（特別是 Humufish 仍有規格未定案）。所以我雖正向看待 Intel 先進封裝長期發展，但中短期內仍會謹慎關注 Intel 如何面對這些挑戰。 【從 90% 到 98%，表面上才差個幾%，Google 會在意嗎？當然會】 1. Google 近期詢問過台積電，自行投片 Humufish 的 main compute die（由 Google 自行設計），與讓聯發科代為投片相較，成本可節省多少。 2. Google 與聯發科的合作一開始（8t）就是採 semi-COT 模式。聯發科的 mark-up 主要來自自行設計部分，所以 Google 是否親自投片 main compute die，不是聯發科獲利成長趨勢的觀察重點。 3. 但從 Google 連投片相關的 pass-through mark-up 都想看看能不能省，代表 Google 的成本控管態度，已從過去的好好先生，變成錙銖必較的精算者，原因在於要跟 Nvidia 直接競爭，所以具備成本優勢的 Google 當然會在意 EMIB-T 生產良率。順帶一提，台積電對 2026 年 5.5-reticle CoWoS 的生產良率目標，也是 98% 起跳。 【台積電的立場】 1. 我的理解是，台積電仍在評估 2H27 要分配多少先進製程產能給 Humufish，原因在於：(1) 仍想爭取後段封裝訂單（但目前看很難，這是 Google 有意為之的策略）、與 (2) 尚在評估後段 EMIB-T 實際產出，避免稀缺的先進製程資源被錯置。 2. 影響 Humufish 後段有效產出的關鍵，包括 EMIB-T 與載板，要追蹤這件事必須兩個一起看。 3. 在 Humufish semi-COT 方面，台積電也是傾向讓聯發科投片main compute die，除了兩家公司關係好外，關鍵是聯發科是台積電第三大先進製程客戶（2025年），若 TPU 訂單有變化，以聯發科的規模，較容易協助台積電做投片組合調整，扮演一個稱職的緩衝角色。

Nvidia LPU/LPX racks set for order-of-magnitude growth: application trends, ecosystem integration, and a new PCB cycle 1. My latest supply-chain checks suggest that following Nvidia’s investment in Groq, LPU shipment forecasts have moved significantly higher. Total shipments in 2026–2027 are estimated at 4–5 million units (with 30–40% in 2026 and 60–70% in 2027). Relative to historical annual volumes, this implies order-of-magnitude growth, roughly 10×+. 2. Fast-growing LPU demand reflects two key factors: (1) Deep integration with Nvidia’s ecosystem (e.g., CUDA), significantly lowering barriers to application development and deployment. (2) Rapid expansion of ultra-low-latency inference workloads, including AI agents (such as coding agents) as well as emerging real-time, consumer-facing, and physical-AI applications. 3. Nvidia is expected to increase LPU density per rack from 64 to 256 units. This helps preserve ultra-low latency during the decode stage of inference while accommodating expanding KV-cache requirements driven by long-context inference. The new rack architecture is expected to enter mass production in 4Q26–1Q27, with rack shipments projected at 300–500 units in 2026 and 15,000–20,000 units in 2027. 4. Three key areas to monitor regarding LPU integration into the Nvidia ecosystem: (1) Network architecture: rack-level interconnect via NVLink Fusion and RealScale. (2) Developer interface: whether Nvidia NIM allows developers to deploy workloads without needing to distinguish between GPUs and LPUs. (3) Compiler integration: whether TensorRT-LLM supports the compile-first architecture of LPUs. 5. The ramp of LPU/LPX racks also has important implications for the PCB supply chain, with WUS Printed Circuit playing a key role. LPU/LPX racks represent the first large-scale deployment of M9-grade CCL materials. A successful ramp would not only contribute meaningfully to WUS’s 2027 earnings, but also confirm the company’s breakthrough in quartz-glass fabric processing for high-layer-count boards—potentially catalyzing a new growth cycle across the PCB industry.

Nvidia LPU/LPX racks set for order-of-magnitude growth: application trends, ecosystem integration, and a new PCB cycle 1. My latest supply-chain checks suggest that following Nvidia’s investment in Groq, LPU shipment forecasts have moved significantly higher. Total shipments in 2026–2027 are estimated at 4–5 million units (with 30–40% in 2026 and 60–70% in 2027). Relative to historical annual volumes, this implies order-of-magnitude growth, roughly 10×+. 2. Fast-growing LPU demand reflects two key factors: (1) Deep integration with Nvidia’s ecosystem (e.g., CUDA), significantly lowering barriers to application development and deployment. (2) Rapid expansion of ultra-low-latency inference workloads, including AI agents (such as coding agents) as well as emerging real-time, consumer-facing, and physical-AI applications. 3. Nvidia is expected to increase LPU density per rack from 64 to 256 units. This helps preserve ultra-low latency during the decode stage of inference while accommodating expanding KV-cache requirements driven by long-context inference. The new rack architecture is expected to enter mass production in 4Q26–1Q27, with rack shipments projected at 300–500 units in 2026 and 15,000–20,000 units in 2027. 4. Three key areas to monitor regarding LPU integration into the Nvidia ecosystem: (1) Network architecture: rack-level interconnect via NVLink Fusion and RealScale. (2) Developer interface: whether Nvidia NIM allows developers to deploy workloads without needing to distinguish between GPUs and LPUs. (3) Compiler integration: whether TensorRT-LLM supports the compile-first architecture of LPUs. 5. The ramp of LPU/LPX racks also has important implications for the PCB supply chain, with WUS Printed Circuit playing a key role. LPU/LPX racks represent the first large-scale deployment of M9-grade CCL materials. A successful ramp would not only contribute meaningfully to WUS’s 2027 earnings, but also confirm the company’s breakthrough in quartz-glass fabric processing for high-layer-count boards—potentially catalyzing a new growth cycle across the PCB industry.

Nvidia LPU/LPX機櫃將迎來數量級成長：應用趨勢、生態整合與PCB新成長週期 1. 我的最新產業調查顯示，Nvidia投資Groq後，LPU出貨規劃大幅上修。2026-2027年LPU共出貨預估約400–500萬顆（2026約30–40%、2027約60–70%），相較過去年度出貨量，將出現10倍以上的數量級成長。 2. LPU需求快速成長主要來自兩項因素： (1) 與Nvidia生態系 (如CUDA) 高度整合，大幅降低應用開發與部署門檻。 (2) 超低延遲推論需求快速增加，包括AI agents（如coding agents）以及正在興起的real-time、consumer-facing與physical-AI等類型應用。 3. 為維持推論decode階段的超低延遲優勢，並因應長文本推理帶動的KV cache需求快速成長，Nvidia預計將每機櫃LPU數量由目前64顆提升至256顆，以擴大記憶體容量並維持超低延遲效能。新架構機櫃預計於4Q26–1Q27量產，2026與2027年機櫃出貨量分別約300–500與15,000–20,000個。 4. Nvidia生態整合LPU的三個關鍵觀察重點： (1) 網路架構：NVLink Fusion與RealScale的機櫃互聯。 (2) 開發者介面：Nvidia NIM是否讓開發者在部署時無需區分GPU與LPU。 (3) 編譯整合：TensorRT-LLM是否支援LPU的compile-first架構。 5. LPU/LPX機櫃量產亦對PCB產業有重要意義，關鍵PCB供應商滬電股份扮演核心角色。LPU/LPX機櫃是首度大規模採用CCL M9材料的應用。若順利量產，不僅意味著LPU方案的數量級成長將在2027年為滬電股份帶來顯著貢獻，也代表該公司突破高層板石英布加工技術門檻，有望帶動PCB產業展開新一輪成長週期。

Nvidia LPU/LPX機櫃將迎來數量級成長：應用趨勢、生態整合與PCB新成長週期 1. 我的最新產業調查顯示，Nvidia投資Groq後，LPU出貨規劃大幅上修。2026-2027年LPU共出貨預估約400–500萬顆（2026約30–40%、2027約60–70%），相較過去年度出貨量，將出現10倍以上的數量級成長。 2. LPU需求快速成長主要來自兩項因素： (1) 與Nvidia生態系 (如CUDA) 高度整合，大幅降低應用開發與部署門檻。 (2) 超低延遲推論需求快速增加，包括AI agents（如coding agents）以及正在興起的real-time、consumer-facing與physical-AI等類型應用。 3. 為維持推論decode階段的超低延遲優勢，並因應長文本推理帶動的KV cache需求快速成長，Nvidia預計將每機櫃LPU數量由目前64顆提升至256顆，以擴大記憶體容量並維持超低延遲效能。新架構機櫃預計於4Q26–1Q27量產，2026與2027年機櫃出貨量分別約300–500與15,000–20,000個。 4. Nvidia生態整合LPU的三個關鍵觀察重點： (1) 網路架構：NVLink Fusion與RealScale的機櫃互聯。 (2) 開發者介面：Nvidia NIM是否讓開發者在部署時無需區分GPU與LPU。 (3) 編譯整合：TensorRT-LLM是否支援LPU的compile-first架構。 5. LPU/LPX機櫃量產亦對PCB產業有重要意義，關鍵PCB供應商滬電股份扮演核心角色。LPU/LPX機櫃是首度大規模採用CCL M9材料的應用。若順利量產，不僅意味著LPU方案的數量級成長將在2027年為滬電股份帶來顯著貢獻，也代表該公司突破高層板石英布加工技術門檻，有望帶動PCB產業展開新一輪成長週期。

Supply chain check update: Nvidia and WUS Printed Circuit have begun testing next-gen CCL material M10, which could trigger the next upgrade cycle in PCB materials for future AI servers. Key points: 1. The program suggests WUS has an early lead in PCB development for Nvidia’s

供應鏈調查更新：Nvidia與滬電股份已開始測試次世代CCL材料M10，將帶動未來AI伺服器的PCB材料新一輪升級週期。幾個重點： 1. 此測試計畫意味著滬電股份在Nvidia次世代機櫃Kyber與新平台 Rubin Ultra / Feynman的PCB之開發上有領先優勢，此優勢有助於該公司未來的營運動能成長。 2.

A few quick thoughts on Apple/iPhone memory price hikes: 1. The 1Q26 LPDDR price hikes mentioned in the news are pretty close to what I’ve heard. NAND flash increases, however, are a bit lower. 2. iPhone memory pricing is now negotiated quarterly instead of every six months, so expect another hike in 2Q26. Right now, the 2Q26 QoQ increase looks similar to 1Q26. 3. For most non-AI brands, even if you’re willing to pay up, there’s no guarantee you’ll get the supply. The fact that Apple can lock in a deal like this shows just how much leverage they have. 4. Higher memory costs will hit iPhone gross margins. But Apple’s playbook is clear: use the market chaos to their advantage—secure the chips, absorb the costs, and grab more market share. They’ll make it back later on the services side. 5. The cost pressure from memory could be a hot topic for investors and analysts at Apple’s earnings call this week. What Apple says could actually shake up other industries’ stocks more than Apple’s own or its suppliers'. 6. Apple’s current plan for 2H26 new iPhone 18 models is to avoid raising prices as much as possible—at least keep the starting price flat, which is helpful for marketing. 7. Apple has realized that it’s not just memory and T-glass—other components could also run short as the AI server boom continues to squeeze the rest of the supply chain.

簡單聊一下Apple/iPhone的記憶體漲價： 1. 這篇新聞提到的1Q26 LPDDR漲價幅度跟我認知的接近，NAND Flash的漲價幅度略低。 2. iPhone的記憶體報價現在是按季談，而非半年，所以iPhone的記憶體報價在2Q26還會再漲一次。目前看2Q26的QoQ漲價幅度約跟1Q26接近。 3. 絕大部分非AI產業的品牌客戶，就算願意付錢也不見得能得到記憶體供應保證，所以Apple能談成這樣已經算很強了。 4. 記憶體報價上漲會影響iPhone的毛利率。但Apple的策略是，趁記憶體市場混亂時，透過確定能拿到貨與吸收成本的優勢，提升市佔率，後續再用服務業務賺回來。 5. 記憶體報價上漲導致成本上升的議題，應該是投資人與分析師對本週Apple法說的關注重點之一。Apple對這件事的說法，可能對其他產業的股價造成的波動，會遠高於對Apple自身與其供應鏈股價的影響。 6. Apple目前對2H26新款iPhone 18的定價策略是「盡可能不漲價」，至少起始價不動，有利行銷宣傳。 7. Apple已經意識到，在記憶體跟T-glass後，可能還會有其他零組件也會受到AI伺服器產業的影響而供應短缺。

My latest supply-chain surveys indicate that Carl Zeiss SMT will significantly expand its EUV and higher-ASP immersion DUV optical system capacity by 20-25% YoY and 40-50% YoY, respectively, in 2027 to meet robust demand from ASML. Coupled with stronger-than-expected shipment

我最新的供應鏈調查顯示，Carl Zeiss SMT (蔡司半導體) 為滿足ASML的強勁需求，將顯著擴增2027年EUV與較高ASP的浸潤式DUV光學系統產能分別約20-25% YoY與40-50% YoY，加上2026年EUV與DUV出貨優於預期，故預估ASML

Wistron, a leading AI server assembler, reported its FY25 financial results. Gross margin (GM) for FY25 and 4Q25 came in at 6.1% and 5.6%, respectively, both below street consensus of 6.5% and 6.8%. 1. These results validate my earlier view on the structural impact of AI server

Regarding recent discussions among CCL-focused investors on whether the key CCL spec for VR200 NVL72 could be downgraded from M9, below are my latest surveys and views: 1. Nvidia previously began testing 896K2 and 892K2 and prototyping PCBs, which likely gave rise to the market rumors. Test results are expected by the end of 1Q26. 2.Nvidia’s current mass-production target remains 896K3. While this has not been finalized, the uncertainty alone is sufficient to impact stock prices that have already priced in this positive expectation. 3. Discussing CPX based on Nvidia’s CES 2026 keynote is somewhat odd, as Jensen didn't mention CPX. CPX currently has lower visibility, potentially due to delays in mass production, but the current target spec remains 896K3. 4. Nvidia’s AI servers continue to push the technological frontier, making extensive testing entirely normal, including previously rumored PTFE from Thaifu and Taichem. 5. This event doesn't change the long-term trend of ongoing upgrades in PCB material spec. 6. The short-term stock price volatility reflects Nvidia’s trade-offs and compromises between real-world constraints and ideal targets. Similar situations are likely to recur in the future.

關於最近關注CCL的投資人討論的VR200 NVL72關鍵CCL規格會否自M9降規，我的最新調查與看法： 1. 先前Nvidia開始測試896K2、892K2並打樣PCB，這可能是市場傳言起源。預計1Q26底前會有測試結果。 2. 目前Nvidia的量產目標依舊是採用896K3。此尚未定案，但此種不確定性足以對已反映此利多的股價造成影響。

Key Updates on NVIDIA Vera Rubin/VR200 NVL72 (Integrating my latest supply chain checks and NVIDIA CEO Jensen Huang’s CES 2026 keynote) 1. NVIDIA has renamed the AI server VR200 NVL144 (die-based) to VR200 NVL72 (package-based). My supply chain checks indicate VR200 NVL72 will be offered in two power profiles: Max Q and Max P. ➢ Jensen referenced NVL72, rather than the previously used NVL144 naming. ➢ Max Q and Max P share the same hardware design. ➢ Max Q GPU/rack power (TGP/TDP): ~1.8/190 (kW). ➢ Max P GPU/rack power (TGP/TDP): ~2.3/230 (kW). ➢ Both are meaningfully higher than GB300 NVL72 at 1.4/140 (kW). ➢ Offering two power profiles improves deployment flexibility under data-center power constraints. It also suggests NVIDIA is increasingly factoring real-world physical infrastructure limits into product specifications. 2. VR200 NVL72 upgrades the GPU thermal solution for both MaxQ and MaxP. ➢ Both use a micro-channel cold plate (MCCP) paired with a gold-plated lid. ➢ The market has been expecting a move to a micro-channel lid (MCL) once GPU TGP reaches 2.3 kW; however, MCL mass production is unlikely before 2H27. 3. Benefiting from upgrades across the GPU, HBM, and NVLink Switch, VR200 NVL72 delivers roughly 3.5×/5× the training/inference AI computing power of GB300 NVL72, driving a sharp increase in rack-level power demand. ➢ VR200 NVL72 upgrades power shelves to 3*3U 110 kW (6*18.3 kW PSUs), vs. the most common GB300 NVL72 configuration of 8*1U 33 kW shelves (6*5.5 kW PSUs). ➢ VR200 NVL72 power shelves adopt an 3+1 redundancy design. ➢ VR200 NVL72 raises the power whip rating to 100A (vs. 60A for GB300 NVL72), tightening data-center power infrastructure requirements (e.g., busway and tap-off boxes). 4. VR200 NVL72 relies even more heavily on liquid cooling. ➢ Both the compute and NVSwitch trays adopt a fanless design. ➢ Rack technology cooling system flow (TCS flow) nearly doubles (~+100%) vs. GB300 NVL72, benefiting spec and/or count upgrades for CDUs, manifolds, cold plates, and quick disconnects (QDs). ➢ Rack airflow requirements fall by roughly 80% (in CFM) vs. GB300 NVL72. 5. VR200 NVL72 compute tray adopts a midplane for the first time, enabling a truly cableless design. ➢ Key midplane specs include 44 layers (22+22), M9 CCL (EM896K3), and an approximate size of 420×60 mm. ➢ Jensen noted that this design can reduce compute-tray assembly time from roughly two hours to about five minutes (vs. GB300 NVL72). 6. Rubin CoWoS are estimated at 300–350k wafers in 2026, with pilot production expected in early 1Q26 and mass production by late 2Q26. VR200 NVL72 rack assembly is expected to enter mass production by the end of 3Q26; factoring in yield ramp, 2H26 rack shipments are estimated at ~5,000–7,000 units. 7. Once rack power approaches ~200 kW, 54V distribution begins to face material constraints in space (busbars/cabling) and conversion efficiency. As a result, VR200 NVL72 can be viewed as the final generation of the Oberon rack architecture. To address the rising rack-power requirements driven by continued AI compute scaling, NVIDIA is expected to transition to the next-generation Kyber rack design, which supports 800V HVDC.

VR200 NVL144 Rail Survey Update Although competition is everywhere—and rails are classified as a higher-replaceability Group C component in Nvidia’s AI server parts categories—my latest supply chain checks indicate that the VR200 NVL144 currently in development, testing, and

VR200 NVL144滑軌調查更新 雖說競爭無所不在，且滑軌在Nvidia的AI伺服器零組件分類中屬於替換程度較高的Group C，但最新的供應鏈調查顯示，目前開發測試組裝中的VR200 NVL144，採用的滑軌是由川湖獨供，料號開頭與GB300 NVL72的相同。

The press release didn’t make it clear that after the first Nvidia Blackwell wafer was produced in the U.S., it would still need to be shipped to Taiwan for CoWoS advanced packaging — only then would the production of the Blackwell chip be considered complete. Two years from now,