Jukan

"Can't Build Equipment Without the Parts"… Semiconductor Test Equipment Faces "Worst-Ever" Supply Crunch The semiconductor test equipment industry is grappling with a severe component shortage—so severe that some are lamenting, "We can't build semiconductor test equipment because there are no semiconductors." According to industry sources on the 29th, the supply of components needed for semiconductor test equipment has become difficult to secure. In particular, lead times for non-memory semiconductors—such as field-programmable gate arrays (FPGAs), central processing units (CPUs), and driver integrated circuits (ICs)—have lengthened dramatically. First, the lead time for the FPGAs needed to operate the equipment has stretched from a previous 8–10 weeks to as much as 52 weeks recently. A distributor source explained, "It varies by FPGA specification, but it's typically 52 weeks," adding that "supply has become difficult to secure." FPGAs are used to analyze test data in real time, quickly identifying problems such as defects. The FPGA market is led by AMD, which acquired Xilinx. The situation is the same for driver ICs used in test equipment. Whereas distributors could previously purchase the relevant chips from inventory immediately, it now takes at least 10 weeks or more. In particular, Analog Devices' (ADI) product lineup for automatic test equipment (ATE) is causing an extreme bottleneck. ADI supplies "pin drivers"—integrated assemblies of multiple devices—for semiconductor test equipment. x86-architecture-based CPUs and graphics processing units (GPUs) are also experiencing supply shortages. One semiconductor equipment industry official noted, "For some products, supply has tightened and unit prices have risen sharply—up to threefold, from a previous 1 million won to 3 million won," adding that "Intel's server CPUs, in particular, are not easy to secure." Intel has recently been allocating its server CPU (Xeon) volumes primarily to high-margin hyperscalers—large-scale cloud service providers—and data center servers. As a result, supply to other markets has been less smooth. Mass production of "Diamond Rapids," the next-generation server CPU, has also been pushed back from the originally planned second half of this year to the middle of next year. Because of this, the development and supply of next-generation equipment that requires the product's high performance and new features have been partially delayed. In fact, one particular test equipment manufacturer recently signed an equipment supply contract worth tens of billions of won with Samsung Electronics, but due to delayed component procurement, it had no choice but to push back the delivery date by three months. An industry official said, "The current situation isn't simply a problem with specific components like FPGAs or CPUs," explaining that "a serious bottleneck is occurring across the entire non-memory semiconductor supply chain." Test equipment manufacturers are responding by placing advance orders for components. Under this approach, they negotiate equipment volumes and delivery dates with customers several months before a formal purchase order (PO) is issued, and order the necessary components ahead of time. Even so, with component delivery delays worsening, fully smooth supply remains difficult to achieve. The industry expects the supply crunch for non-memory components used in test equipment to persist for some time. This is because the boom in downstream industries—such as demand for AI and data center infrastructure—continues, driving up demand for semiconductors (components) and semiconductor test equipment simultaneously. Semiconductor manufacturers that purchase test equipment are also on high alert. As one industry official put it, "A strategy in which semiconductor manufacturers and equipment makers cooperate closely to respond proactively is increasingly becoming the new normal."

Samsung Electronics: "Taylor Fab Ready for Operation... Mass Production Next Year" Samsung Electronics has reaffirmed that it will begin ramp production at its Taylor fab in Texas, USA, starting next year. Margaret Han, Vice President of Samsung Electronics' Foundry U.S. division, stated at the SAFE (Samsung Advanced Foundry Ecosystem) Forum held at Samsung's U.S. headquarters on the 28th (local time), "Customers will begin production at the Taylor fab starting next year," adding, "We are ready." Previously, during the first-quarter earnings conference call this year, Samsung had described the Taylor fab as "under construction," with a goal of timely operation within the year. Construction of the Taylor fab began in 2022. The total expected investment is $17 billion (approximately ₩25.5 trillion), and it will produce Tesla's autonomous-driving chips AI5 and AI6, among others. The fab will also adopt the Advanced 2nm process. Han said, "We will strengthen our long-term production capacity at the Taylor fab," and "We will establish the most advanced 2nm production capacity at Taylor Fab 1 this year." Samsung is analyzed to be building out the SF2P+ (second-generation enhancement) process at the Taylor fab. Samsung had previously announced that SF2P+ would enter operation in 2026–2027. The 2nm process is divided into SF2 (first generation), SF2P (second generation), SF2P+, and SF2X (third generation for AI/HPC), among others. With each successive generation, power, performance, and area (PPA) improve. SF2P+ is a process that improves PPA while maintaining the same design IP as SF2P. It has been finely tuned for AI workloads. Performance is reportedly improved by up to 30%. Detailed information on the leading-edge processes is scheduled to be shared with partner companies this coming July. Samsung will hold the SAFE Forum again at its Seocho headquarters in July. The SAFE Forum is an occasion where Samsung and its foundry partners share technology trends across fields such as IP, design, and packaging, and strengthen collaboration. Later that same month, Samsung is reported to host the Samsung Foundry Forum (SFF). The Foundry Forum is an event where Samsung unveils its foundry technology roadmap to partner companies.

Rumor: Nvidia plans to invest NT$20 billion (US$620 million) for a stake in Taiwan ABF substrate supplier Kinsus Interconnect, media report. $NVDA #Kinsus

Samsung Electronics Eyed for Anthropic Chip Order… Foundry Revival Begins Samsung Electronics has made an investment in Anthropic, the U.S. AI company behind the AI model "Claude," raising the possibility of a foundry partnership in which Samsung would manufacture Anthropic's

Micron EVP and Chief Business Officer Sumit Sadana: Even with all the new investments, meaningful memory chip supply will only start coming online in late 2027 and ramp up in 2028. $MU

Bruh, according to Geekerwan’s TEM analysis, Samsung’s 2026 SF2 still lags slightly behind Intel’s 2025 18A in terms of geometry control and process consistency. $INTC

Rosenblatt InP lasers checks: According to our checks, NVIDIA, which is the driving force behind scale up CPO, asked the supply chain to increase InP laser capacity by ~20x from 2025-2030. The vendors appear to have taken a more conservative stance, agreeing to an ~12x increase ( $AAOI / $LITE etc)

JENSEN HUANG: “WE HAVE A SURPRISING NEW PRODUCT THAT WE HAVEN’T TOLD ANYONE ABOUT YET. WE WILL ANNOUNCE IT LATER.”

Intel Accelerates Foundry Revival, Spearheaded by Advanced Packaging Intel is accelerating the revival of its foundry (contract manufacturing) business through large-scale investment in advanced semiconductor packaging. By expanding infrastructure such as materials, components, and equipment, Intel is significantly scaling up its advanced packaging capacity to strengthen its response to the foundry customers it has recently secured. According to industry sources on the 28th, Intel is currently placing large-scale purchase orders for materials, components, and equipment from its global supply chain partners. Multiple supply contracts for materials, components, and equipment have reportedly already been signed. Some Korean materials/components/equipment companies are also participating. An industry official familiar with the matter said, "Advanced packaging facility investment on the scale of several trillion won is underway," adding, "Considering equipment lead times and the timing of materials and component supply, full-scale operation is expected next year." Intel is also discussing cooperation with some partners regarding facility investment in 2028. The investment locations cited as major packaging production hubs include the United States as well as Vietnam and Malaysia. This investment is said to be focused on expanding capacity for "EMIB (Embedded Multi-die Interconnect Bridge)." EMIB is Intel's proprietary 2.5D packaging technology that connects different semiconductors (dies). Signals are exchanged between chips via a silicon bridge embedded in the semiconductor substrate, and it is known to offer superior cost and productivity compared to the silicon interposer-based 2.5D packaging led by TSMC. In particular, it enables precise 2.5D packaging by connecting only the necessary areas with bridges. Intel is advancing EMIB further with technologies such as EMIB-T, which applies through-silicon via (TSV) technology to the bridge, and packaging that integrates glass substrates. The aim is to broaden its customer base by diversifying its packaging technologies. This materials/components/equipment investment also includes numerous new technologies to be applied to next-generation packaging. This packaging investment is a strategic move to strengthen foundry capabilities. Intel declared its re-entry into the foundry business in 2021 and pursued the development of advanced (front-end) processes, but it has struggled to secure major customers. This was largely due to TSMC's dominance in advanced chip foundry, including AI semiconductors. The packaging investment is also interpreted as a strategy to strengthen Intel's differentiated capabilities to attract foundry customers. Because the limits of circuit miniaturization mean the entire industry faces constraints in boosting chip performance through front-end processes, Intel is seen as attempting to break through this bottleneck with advanced packaging (back-end) and place its entire foundry business on a stable trajectory. Intel is also pursuing front-end advancement in parallel to maximize synergy. Last year, Intel brought its "Intel 18A" process—equivalent to the 2-nanometer (㎚) class—into full-scale operation. It has continued facility investment not only for its own chips but also to serve foundry customers. Another industry official predicted, "This packaging investment is evidence that Intel has secured a certain degree of advanced foundry process customers," and "The 18A process combined with expanded advanced packaging investment could be the starting signal for Intel's foundry revival." $INTC

Intel’s EMIB Packaging Is Growing Rapidly — Silicon Capacitors Are Taking Off Too Silicon capacitors are poised for explosive growth in the AI semiconductor space. Intel has been found to be planning a large-scale adoption of silicon capacitors starting next year, in order to enhance the performance of its in-house 2.5D packaging technology, “EMIB.” The most clearly visible source of demand is Google. Google plans to launch its next-generation AI accelerator, “v8e,” in the second half of next year, and has adopted an EMIB substrate with embedded silicon capacitors for that chip. With other Big Tech companies such as Amazon also currently applying EMIB, analysts say demand could increase sharply. According to industry sources on the 27th, Intel plans to apply silicon capacitors to its 2.5D packaging starting next year. Intel Adopts “Silicon Capacitors” for 2.5D Packaging… Google AI Chip Gets First Application 2.5D is an advanced packaging technology that inserts a thin-film interposer between the semiconductor and the substrate. Because it can connect circuits at higher density compared with conventional packaging that uses only a substrate, demand is rising in the AI and HPC fields. To improve cost efficiency in 2.5D packaging, Intel devised its own technology called EMIB. Rather than using a broad, spread-out interposer, EMIB connects chip to chip using a small silicon bridge. Since bridges only need to be placed where chip-to-chip connections are required, chips can be arranged more flexibly and efficiently. Recently, EMIB has been drawing attention as an alternative to TSMC, which had been leading the existing 2.5D packaging market. This is because TSMC’s 2.5D packaging capacity is suffering from a supply shortage amid the rapid development of the AI industry. Indeed, global Big Tech player Google is also paying attention to EMIB. Google has decided to adopt EMIB for its in-house AI semiconductor “v8e,” which it plans to launch in the second half of next year. Under this structure, TSMC handles chip mass production, MediaTek handles design and manufacturing support, and Intel handles packaging. However, there have been concerns that EMIB is gradually showing limitations in providing stable power supply for AI semiconductors, which consume large amounts of power. Accordingly, Intel plans to introduce new technologies such as silicon capacitors and through-silicon vias (TSV) to ensure stable packaging for the v8e. A capacitor is a component that stores and releases electricity in an electronic circuit. In the case of silicon capacitors, their resistance (ESL/ESR) is more than 100 times lower than that of conventional multilayer ceramic capacitors (MLCC), minimizing the signal loss that occurs in high-performance semiconductors. They can also be designed in an ultra-thin structure based on a silicon wafer, enabling high-density integration. A semiconductor industry official explained, “Because the voltage drop (the phenomenon of voltage decreasing) that occurs in the high-frequency region within AI chips is difficult to solve with MLCC, we understand that Intel is adopting silicon capacitors as a solution,” adding, “The relevant supply chain is now in place, and mass production is set to begin in earnest next year.” EMIB-T Is Already on a Growth Trajectory — The Related Ecosystem and Market Are Expanding Together Intel has also inserted TSVs, which serve as power-delivery channels, into the silicon bridge. The key point is that by using TSVs to shorten the power-delivery path between the substrate and the chip, Intel has improved power efficiency and signal integrity. Intel calls this “EMIB-T.” The industry expects the EMIB-T and silicon capacitor markets to grow rapidly. This is because Japan’s Ibiden — one of the major companies that mass-produces semiconductor substrates for EMIB-T — is aggressively pursuing capital investment. Previously, Ibiden had planned to build its Kawashima (Gama) plant in Gifu Prefecture as a substrate plant for Intel CPUs. However, it postponed that schedule and decided in the first half of this year to officially convert the Gama plant into a mass-production line for EMIB-T substrates. The investment is 220 billion yen (about KRW 2.1 trillion). In its recent earnings announcement, Ibiden stated, “Operation of the Gama plant will begin in 2027 and enter full-scale mass production in 2028,” adding, “EMIB-T substrate capacity is currently far short of demand. However, adding further capacity is quite difficult, so we are discussing options with our customers.” A semiconductor industry official explained, “Ibiden’s EMIB-T-dedicated line is being built with most of the investment coming from customers such as Google, Amazon, and Intel,” adding, “This demonstrates that AI semiconductors based on EMIB-T will grow significantly going forward, and silicon capacitors are likely to expand alongside them.”

I really wish I could’ve been there to hear C.C. Wei speak directly about the union and Elon. It’s a shame I couldn’t attend.

So JPM is using my tweets in their reports — I just found out today.

JPM: Another beneficiary of the AI cycle is European luxury stocks The report argues that the AI supercycle has driven a surge in HBM and memory demand, sharply improving earnings expectations for Samsung Electronics and SK hynix. This, in turn, has supported equity-market strength, with the KOSPI up 91% year-to-date, bolstering consumer sentiment and high-end consumption. While Korean households’ allocation to equities, bonds, and funds is only around 4%, lower than in the U.S. or Western Europe, the magnitude of the market rally means the wealth effect is still meaningful. JPM also estimates that the after-tax bonus pools at Samsung Electronics and SK hynix alone could reach roughly $25 billion in 2026 and more than $35 billion in 2027. JPM expects this wealth effect to be particularly concentrated among younger male consumers. Given that roughly two-thirds of Samsung Electronics and SK hynix employees are male, the categories most likely to benefit first are luxury cars, watches, high-end ready-to-wear, and outerwear. Leather goods and jewelry, which are more female-oriented categories, could also benefit, but more through gifting demand than direct consumption.

Things I’ve looked into recently: I’m increasingly convinced that semiconductor equipment could become seriously scarce going forward. Based on channel checks, the “tera-fab” project appears to be much more serious than expected. Intel needs to absorb foundry customers from TSMC while also expanding capacity for its own CPUs. Samsung also seems to have recently secured multiple customers. And TSMC may raise its capex guidance in Q3 this year. SK hynix appears to be performing better than Samsung in HBM4. HBM price renegotiations do not seem to be going smoothly. Hyperscalers appear very reluctant to renegotiate the prices under the long-term agreements they signed last year.

[Exclusive] NVIDIA's "Rubin CPX" Launch in Doubt… No Memory or Substrate Orders The launch of NVIDIA's inference GPU "Rubin CPX" has become uncertain. Although the company had initially announced plans to release it in the second half of this year, it has been confirmed that there are no moves to order or develop the associated memory and substrates. This has led to speculation that NVIDIA may have withdrawn or substantially revised its original plans. According to multiple industry sources on the 27th, NVIDIA is currently not placing orders for memory or substrates related to Rubin CPX. In particular, no activity has been confirmed around GDDR7 graphics DRAM, the memory it was reported to use. Nor have there been any related development requests. A memory industry source said, "NVIDIA stated that it would use GDDR7 in Rubin CPX, but at the moment there are no discussions about it whatsoever," adding, "There was also a possibility that HBM adoption was being considered, but with no progress made, the actual development direction is unclear." A substrate industry source said, "With no movement around Rubin CPX, the industry effectively regards the project as cancelled," adding, "We had expected GDDR7's range of applications to expand, but it's disappointing that the market never opened up." NVIDIA announced at the AI Infra Summit last September that it would release Rubin CPX in the second half of this year. It specifically stated that Rubin CPX would carry a total of 128GB of GDDR7 memory — a configuration of eight 16GB GDDR7 chips. Unlike high-bandwidth memory (HBM), which is mounted inside the GPU package, it was planned to use an onboard approach, with the memory placed around the GPU substrate. Because inference AI servers do not require the extreme memory bandwidth that training GPUs do, GDDR memory was adopted. HBM offers fast data processing but carries heavy cost and power burdens, and is also more difficult to package. GDDR, by comparison, has a relatively lower cost burden and is easier to scale in supply. The memory industry had expected that Rubin CPX would trigger a full-scale expansion in GDDR7 supply. Currently, GDDR7 is used mainly in a handful of high-performance graphics cards such as NVIDIA's GeForce RTX 5090 and 5080, leaving its applications limited. The substrate industry likewise anticipated benefiting from expanded supply of memory substrates for GDDR7. However, NVIDIA removed Rubin CPX from its roadmap at GTC 2026, held this past March — a change in direction roughly six months after it was unveiled with a second-half launch target. Some foreign media outlets asked about the reasons behind this, but NVIDIA offered no answer. Instead, the company put front and center the LPU (Language Processing Unit) from Groq, with which it signed a licensing agreement late last year. The "Groq 3 LPX" abruptly became the core inference product of the Vera Rubin platform. Last year, NVIDIA struck a deal worth $20 billion with Groq and absorbed its core inference technology and engineering talent. The industry views this as NVIDIA having effectively acquired Groq. Rubin CPX was a product NVIDIA had been preparing in response to the expanding inference market. Whereas NVIDIA's existing GPUs focused on large-scale data training, Rubin CPX was specialized for inference — the execution stage of AI services. It was a strategy aimed at a market shift in which inference computing is taking up a growing share amid the spread of AI agents. As NVIDIA strengthens its Groq-centered inference strategy, observers suggest that the very direction of Rubin CPX may have changed. Some also raise the possibility that NVIDIA could redesign Rubin CPX in a new form down the line. $NVDA

"Likely SpaceX Win for new datacenter ASIC. We expect MTK to be the design service provider for xAI’s datacenter ASIC based on Intel 14A + EMIB-T." Interesting....

Just in: SK Hynix’s market cap has surpassed $1 trillion.

SK Hynix Effectively Rebuffs US Big Tech's Offers of Tens of Billions of Dollars in Investment Support US big tech companies—Google parent Alphabet, Microsoft (MS), and Meta among them—are pouring out offers to help fund the construction of fabs (chip plants) worth tens of trillions of won and to cover the cost of purchasing extreme ultraviolet (EUV) lithography equipment. But SK Hynix is politely declining these offers while simultaneously using them as leverage in long-term supply agreements. The reasoning: with investment funds already overflowing, there is no reason to disturb the "super supplier" (super-eul) status it currently enjoys. According to industry sources on the 27th, SK Hynix recently received memory-chip capital-investment support offers from Alphabet, MS, and Meta, but management is reportedly not treating them as realistic, actionable options. The biggest sticking point is that building a fab with funding from a specific big tech company would create a contract structure carrying exclusive supply obligations. A semiconductor industry official said, "If you build a production line with a particular customer's money, you create the risk that even if that customer's demand falls in a future downturn, you'd have to prioritize their volume or supply below market price," adding, "Internally, SK Hynix views the side effects that could arise from taking big tech investment negatively and is wary of them." SK Hynix currently holds what is effectively a duopoly alongside Samsung Electronics in the high-bandwidth memory (HBM) market. It supplies most of the HBM mounted on Nvidia graphics processing units (GPUs), and this year's output is already sold out. Because there are virtually no producers other than SK Hynix and Samsung capable of properly mass-producing the high-spec HBM used in AI data centers, a reversal has taken shape in which the big tech customers have instead become the subordinate party (eul) before SK Hynix. The big tech proposals take two main forms. The first is to directly shoulder part of the cost of building the first fab (Y1) in the semiconductor cluster SK Hynix is developing in Yongin, Gyeonggi Province. SK Hynix plans to invest a total of 31 trillion won in the first fab alone; once completed, it will add 350,000 wafers per month of production, expanding total capacity to around 900,000 wafers per month. Also under discussion was a plan to subsidize the cost of purchasing EUV lithography equipment from the Netherlands' ASML. ASML's latest High-NA EUV machine is an ultra-premium tool costing roughly $400 million (about 550 billion won) per unit—about twice as expensive as the current-generation EUV. To secure this equipment, which is essential for mass-producing advanced memory at the 1c DRAM node and beyond, SK Hynix has already finalized a plan to bring in some 12 trillion won worth of EUV tools. The move is read as big tech's intent to effectively pre-secure dedicated production lines by sharing part of this cost. Behind the unusual nature of these proposals lies the extreme intensification of the AI infrastructure investment race. Alphabet, Meta, and MS each disclosed AI infrastructure investment plans worth tens of billions of dollars in their recent earnings reports. MS in particular said its capital expenditure this year would reach $190 billion, explaining that the increase in component costs such as chips alone amounts to $25 billion. Meta likewise acknowledged its supply-chain pre-emption strategy, saying it is signing contracts across the supply chain to secure necessary components in advance. SK Hynix is refusing structural dependence—such as fab equity investment or joint equipment ownership—while opting instead to use big tech's desperation as negotiating leverage. A source familiar with SK Hynix said, "Various ideas are being discussed to strengthen the binding force of contracts as we sign long-term agreements (LTAs) with global big tech." The industry interprets this as higher prepayments, ultra-long contracts of five years or more, and price-floor guarantee clauses. The strategy is to convert the funds big tech brings not into factory equity, but into more favorable contract terms. SK Hynix's confidence is backed by the numbers. Its operating margin as of the first quarter this year reached 72%, and in February it announced an additional $15 billion (about 21 trillion won) investment plan to expand next-generation memory production. Construction of the first fab at the Yongin cluster is under way, targeting its first cleanroom operation in February next year—three months ahead of the original schedule. $MU $DRAM

Exclusive: TSMC’s 3nm prices said to rise 15% in the second half; another 10% hike possible next year. C.C. Wei expected to “make things clear” at the shareholders’ meeting. $TSM $INTC

Holy Stone Enterprise says AI power surge will deepen global MLCC shortages • Taiwan’s Holy Stone expects global MLCC supply to tighten further on the back of AI power-spec upgrades, with lead times already extending to 20+ weeks. • The company assesses that the proliferation of AI applications is driving the strongest MLCC demand in the past 20 years, and anticipates the supply shortage to deepen through 2027. • On robust demand from AI power customers, production lines remain fully utilized; a Phase 2 capacity expansion is underway, with new equipment to be installed in stages in 3Q26 and 1Q27. • Following the equipment setup period, the company targets a 20–30% capacity increase by end-2026, with a further 30–40% expansion in 2027. • Driven by growing demand for high-spec MLCCs—centered on low-loss NP0 and mid-/high-voltage X7R products—upstream equipment lead times have lengthened to roughly 1–1.5 years. • A scramble to secure equipment similar to the 2018 MLCC expansion cycle is unfolding, but the company notes the key difference this cycle is that an AI-led improvement in the high-spec product mix is accompanied by a supply shortage. • The generational transition of AI platforms—Nvidia A100 (2020) → H100 (2022) → Blackwell (2026) → Vera Rubin (volume production slated for Q4) → Rubin Ultra (2027)—and the accompanying architectural shifts are expected to sustain growing demand for high-spec MLCCs. • The company has entered the supply chains of the four major U.S. CSPs and Dell, and is pursuing a strategy of product-spec upgrades rather than price hikes. • With the pace of new capacity additions limited, the company plans to scale back shipments of low-/mid-end products; going forward, the expansion of new markets such as AI data centers, BBUs, humanoids, and eVTOLs is expected to drive rising high-spec MLCC penetration and structural improvement across the industry over the next 3–5 years.

Intel’s Lip-Bu Tan is reportedly set to arrive in Taiwan this week for a visit to TSMC. $INTC $TSM

Huawei's latest announcement carries real significance, because China has, in effect, shown the direction in which advanced technology needs to move. And it has done so in cutting-edge semiconductors, no less. China has long been a follower. In semiconductors, Western technology played the role of the pioneer, while China was preoccupied with simply keeping pace. But by banning EUV exports to China, the U.S. manufactured a bottleneck at the lithography tool — and in doing so, it effectively forced creativity onto China. To circumvent the sanctions, China was pushed toward approaches the West had never needed to take. That is exactly what today's announcement represents. Where Nvidia co-designs memory, packaging, and logic to optimize TCO at the system level — doing it rack by rack — Huawei is doing the same thing at the chip level. I'll say it again: this is a genuinely striking approach. Memory makers are already struggling with cost scaling. As linewidths shrink, the resources required to keep shrinking them — capital, manpower, time — are climbing exponentially. So the day will come when the West, too, must make packaging, logic, and memory collaborate from the node-design stage. And it won't be far off. China, through the paradox of sanctions, has been driven to do this ahead of the West — unintentionally. This is what genuinely frightens me. As YMTC has already demonstrated, U.S. sanctions pushed China to skip the incumbent standard and jump straight to the next-generation one. The result? YMTC carved out a meaningful presence in hybrid bonding — and even Samsung, the king of NAND, ended up licensing YMTC's patents. I believe the West may well find itself licensing this Huawei technology a few years down the road. And I believe cases like these will multiply, spreading China-style standards in their wake.

Samsung Electronics Achieves World's First "900-Layer V-NAND"… Countdown to the 1,000-Layer Era Samsung Electronics has become the world's first to successfully implement a prototype of 900-layer-class V-NAND technology, taking another step toward the era of "1,000-layer NAND."

Very interesting. With Samsung and SK Hynix delaying V10 NAND mass production to next year, if Kioxia successfully ramps V10 NAND next year, the technology gap between Samsung/SK Hynix and Kioxia would narrow significantly.

Dell is up a lot today… Dell has significant growth potential thanks to CPUs. CPU servers for Agentic AI share many components with general-purpose servers, but come with a higher ASP. This is a major tailwind for Dell, given its strength in general-purpose servers. $DELL